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1 ltc1325 microprocessor-controlled battery management system features descriptio n u n fast charge nickel-cadmium, nickel-metal-hydride, lithium ion or lead-acid batteries under m p control n flexible current regulation: C programmable 111khz pwm current regulator with built-in pfet driver C pfet current gating for use with external current regulator or current limited transformer n discharge mode n measures battery voltage, battery temperature and ambient temperature with internal 10-bit adc n battery voltage, temperature and charge time fault protection n built-in voltage regulator and programmable battery attenuator n easy-to-use 3- or 4-wire serial m p interface n accurate gas gauge function n wide supply range: v dd = 4.5v to 16v n can charge batteries with voltages greater than v dd n can charge batteries from charging supplies greater than v dd n digital input pins are high impedance in shutdown mode the ltc ? 1325 provides the core of a flexible, cost-effec- tive solution for an integrated battery management sys- tem. the monolithic cmos chip controls the fast charging of nickel-cadmium, nickel-metal-hydride, lead-acid or lithium batteries under microprocessor control. the de- vice features a programmable 111khz pwm constant current source controller with built-in fet driver, 10-bit adc, internal voltage regulator, discharge-before-charge controller, programmable battery voltage attenuator and an easy-to-use serial interface. the chip may operate in one of five modes: power shut- down, idle, discharge, charge or gas gauge. in power shutdown the supply current drops to 30 m a and in the idle mode, an adc reading may be made without any switching noise affecting the accuracy of the measurement. in the discharge mode, the battery is discharged by an external transistor while the battery is being monitored by the ltc1325 for fault conditions. the charge mode is termi- nated by the m p while monitoring any combination of battery voltage and temperature, ambient temperature and charge time. the ltc1325 also monitors the battery for fault conditions before and during charging. in the gas gauge mode the ltc1325 allows the total charge leaving the battery to be calculated. n system integrated battery charger applicatio n s u typical applicatio n u , ltc and lt are registered trademarks of linear technology corporation. battery charger for up to 8 nicd or nimh cells 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 v dd pgate dis v bat t bat t amb v in sense filter ltc1325 reg d out d in cs clk ltf mcv htf gnd + r1 c reg 4.7 m f therm 2 therm 1 r5 r dis r trk r sense ltc1325 ?ta01 l1 62 m h bat n1 irfz34 v dd 4.5v to 16v r13 r2 r3 r4 c f 1 m f mpu (e.g. 8051) p1.4 p1.3 p1.2 + c2 10 m f + c reg 22 m f c1 0.1 m f 100 d1 1n6818 p1 irf9730
2 ltc1325 symbol parameter conditions min typ max units v dd v dd supply voltage l 4.5 16 v i dd v dd supply current all ttl inputs = 0v or 5v, no load on reg l 1200 2000 m a i pd v dd supply current power-down mode, all ttl inputs = 0v or 5v l 30 50 m a v reg regulator output voltage no load l 3.047 3.072 3.097 v ld reg regulator load regulation sourcing only, i reg = 0ma to 2ma C 1 C 5 mv/ma li reg regulator line regulation no load, v dd = 4.5v to 16v C 60 C 100 m v/v tc reg regulator output tempco no load, 0 c < t a < 70 c 50 ppm/ c v dac dac output voltage vr1 = 1, vr0 = 1, 100% duty ratio, i chrg = i (note 7) 140 160 180 mv vr1 = 1, vr0 = 0, 100% duty ratio, i chrg = i/3 48 55 62 mv vr1 = 0, vr0 = 1, 100% duty ratio, i chrg = i/5 30 34 38 mv vr1 = 0, vr0 = 0, 100% duty ratio, i chrg = i/10 16 18 21 mv v hyst fault comparator hysteresis v htf = 1v, v edv = 0.9v, v batr = 100mv 20 mv v mcv = v ltf = 2v 10 mv v os fault comparator offset v htf = 1v, v edv = 0.9v, v batr = 100mv 50 mv v mcv = v ltf = 2v v batr v bat for batr = 1 100 mv v batp v bat for batp = 1 l v dd C 1.8 v v edv internal edv voltage l 860 900 945 mv v ltf , v mcv ltf, mcv voltage range 1.6 2.8 v v htf htf voltage range 0.5 1.3 v a gg gas gauge gain C 0.4v < v sense < 0v C 4 v os(gg) gas gauge offset C 0.4v < v sense < 0v (note 6) 1 lsb r f internal filter resistor 1000 w tol batd battery divider tolerance all division ratios l C2 2 % v il input low voltage clk, cs, d in l 0.8 1.3 v v ih input high voltage clk, cs, d in l 1.7 2.4 v i il low level input current v clk , v cs or v din = 0v l C 2.5 2.5 m a i ih high level input current v clk , v cs or v din = 5v l C 2.5 2.5 m a electrical characteristics order part number absolute m axi m u m ratings w ww u package/order i n for m atio n w u u consult factory for industrial and military grade parts. v dd = 12v 5%, t a = 25 c, unless otherwise noted. (notes 1, 2) v dd to gnd ............................................................. 17v all other pins ................................ C 0.3v to v dd + 0.3v operating temperature range ..................... 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 5 6 7 8 9 top view n package 18-lead pdip 18 17 16 15 14 13 12 11 10 reg d out d in cs clk ltf mcv htf gnd v dd pgate dis v bat t bat t amb v in sense filter sw package 18-lead plastic so wide t jmax = 125 c, q ja = 75 c/ w (n) t jmax = 125 c, q ja = 100 c/ w (sw) ltc1325cn ltc1325csw
3 ltc1325 v dd = 12v 5%, t a = 25 c, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units t hdi hold time, d in after clk - 150 ns t dsucs setup time, cs before first clk - 1 m s t dsudi setup time, d in stable before first clk - 400 ns t whclk clk high time 0.8 m s t wlclk clk low time 1 m s t whcs cs high time between data transfers 1 m s t wlcs cs low time during data transfer msbf = 1 43 clk cycles msbf = 0 52 clk cycles reco e ded characteristics uww the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to the gnd pin. note 3: v reg within specified min and max limits, clk (pin 5) = 500khz, unless otherwise stated. adc clock is the serial clk. note 4: linearity error is specified between the actual end points of the a/d transfer curve. note 5: channel leakage is measured after channel selection. note 6: gas gauge offset excludes a/d offset error. note 7: i = v dac (duty ratio)/r sense , where v dac is the dac output voltage with control bits vr1 = vr0 = 1, duty ratio = 1 and r sense is determined by the user. symbol parameter conditions min typ max units v ol output low voltage d out , i out = 1.6ma l 0.4 v v oh output high voltage d out , i out = C 1.6ma l 2.4 v i oz hi-z output leakage v cs = 5v l 10 m a v ohfet dis or pgate output high v dd = 4.5v to 16v l v dd C 0.05 v v olfet dis or pgate output low v dd = 4.5v to 16v l 0.05 v t ddo delay time, clk to d out valid see test circuits l 650 ns t dis delay time, cs - to d out hi-z see test circuits l 510 ns t en delay time, clk to d out enabled see test circuits l 400 ns t hdo time d out remains valid after clk see test circuits l 30 ns t rdout d out rise time see test circuits l 250 ns t fdout d out fall time see test circuits l 100 ns f clk serial i/o clock frequency clk pin l 25 500 khz t rpgate pgate rise time c load = 1500pf l 150 ns t fpgate pgate fall time c load = 1500pf l 150 ns f osc internal oscillator frequency charge mode, fail-safes disabled 90 111 130 khz a/d converter offset error v in channel (note 3) l 2 lsb linearity error v in channel (notes 3, 4) l 0.5 lsb full-scale error v in channel (note 3) l 1 lsb on-channel leakage v in channel on only (notes 3, 5) l 10 m a off-channel leakage v in channel off (notes 3, 5) l 10 m a
4 ltc1325 typical perfor m a n ce characteristics uw load current (ma) 0 regulator output voltage (v) 3.074 3.075 3.076 3.0 1325 g01 3.073 3.072 0.5 1.0 1.5 2.5 3.5 2.0 4.0 3.071 3.070 3.077 v dd = 12v v dd = 4.5v v dd = 16v t a = 27 c temperature ( c) 0 0 shutdown current ( m a) 5 15 20 25 20 40 50 90 1325 g06 10 10 30 60 70 80 v dd = 12v v dd = 16v v dd = 4.5v temperature ( c) 0 v dd supply current ( m a) 1000 900 800 700 600 500 400 300 200 100 0 20 40 50 90 1325 g03 10 30 60 70 80 v dd = 16v v dd = 4.5v v dd = 12v dac output voltage vs temperature temperature ( c) 0 3.072 3.073 3.075 3.076 3.077 3.082 3.079 20 40 50 90 1325 g02 3.074 3.080 3.081 3.078 10 30 60 70 80 v dd = 16v i reg = 0 v dd = 4.5v regulator output voltage (v) v dd = 12v fault comparator threshold vs temperature fault comparator threshold vs temperature temperature ( c) 0 fault comparator threshold (v) 11 10 9 8 7 6 5 4 3 2 1 20 40 50 1325 g08 10 30 60 70 80 v bat for batp = high, v dd = 12v v cell for mcv = high, v mcv = 2.8v and v tbat for ltf = high, v ltf = 2.8v v tbat for htf = high, v htf = 1.35v v cell for mcv = high, v mcv = 1.6v v tbat for ltf = high, v ltf = 1.6v gas gauge gain and offset vs temperature v dd supply current vs temperature temperature ( c) 0 4.5 gas gauge gain and offset (counts) 4.0 ?.0 2.5 ?.0 70 60 0 1325 g09 3.5 10 20 30 40 50 80 ?.5 ?.0 0.5 v sense = 0.2v and 0.4v includes changes in v reg with temperature gas gauge offset gas gauge gain charge current vs battery voltage regulator output voltage vs load current regulator output voltage vs temperature temperature ( c) 0 dac output voltage (mv) 180 160 140 120 100 80 60 40 20 0 30 50 1325 g05 10 20 40 60 70 v dd = 12v vr1 = 1, vr0 = 1 vr1 = 1, vr0 = 0 vr1 = 0, vr0 = 0 vr1 = 0, vr0 = 1 shutdown current vs temperature battery voltage (v) 0 charge current (ma) 160 140 120 100 80 60 40 20 0 2 468 1325 g04 10 12 vr1 = 1, vr0 = 1 vr1 = 1, vr0 = 0 vr1 = 0, vr0 = 0 vr1 = 0, vr0 = 1 v dd = 12v, r sense = 1 w , l = 100 m h, p1: irf9531 temperature ( c) 0 0 fault comparator threshold (v) 0.1 0.3 0.4 0.5 1.0 0.7 20 40 50 1325 g07 0.2 0.8 0.9 0.6 10 30 60 70 80 v cell for edv = high v tbat for htf = high, v htf = 0.4v v cell for batr = high
5 ltc1325 typical perfor m a n ce characteristics uw load capacitance (nf) 0 pgate rise time (ns) 400 800 1200 1000 600 200 4 8 12 16 1325 g10 20 2 0 6 10 14 18 t a = 0 c t a = 70 c t a = 27 c load capacitance (nf) 0 pgate fall time (ns) 600 800 1000 900 700 500 300 100 16 ltc1325 g11 400 200 0 4 2 6 10 14 18 8 12 20 t a = 70 c t a = 0 c t a = 27 c pgate fall time vs load capacitance code 0 differential nonlinearity (lsb) 1024 1325 g12 256 512 768 1.0 0.5 0 0.5 1.0 128 384 640 896 v dd = 12v f clk = 500khz load capacitance (nf) 0 0 discharge rise and fall time ( m s) 2 6 8 10 14 2 10 14 1325 g13 4 12 8 18 20 4 6 12 16 t a = 70 c t a = 27 c t a = 0 c rise time fall time code 0 integral nonlinearity (lsb) 1024 1325 g15 256 512 768 1.0 0.5 0 0.5 1.0 128 384 640 896 v dd = 12v f clk = 500khz integral nonlinearity temperature ( c) ?0 108 oscillator frequency (khz) 109 111 112 113 118 115 0 40 60 1325 g16 110 116 117 114 ?0 20 80 100 oscillator frequency vs temperature temperature ( c) 0 clk to d out valid delay time (ns) 400 500 600 60 1325 g18 300 200 10 20 30 50 70 40 80 100 0 700 d out going high d out going low clk to d out enable delay time vs temperature clk to d out valid delay time vs temperature temperature ( c) 0 0 clk to d out enable delay time (ns) 50 150 200 250 500 350 20 40 50 1325 g17 100 400 450 300 10 30 60 70 80 number of cells 1 minimum charge voltage (v) 7 1325 g14 35 16 14 12 10 8 6 4 2 0 2468 r sense = 1, vr1 = 1, vr0 = 1 l = 25 m h to 100 m h irf9z30pfet, 1n5819 diode r sense = 0.15, vr1 = 1,vr0 = 1 l = 10 m h to 100 m h irf9z30pfet, 1n5819 diode t a = 27 c, nicd batteries v cell = 1.4v nominal discharge rise and fall time vs load capacitance minimum charging supply vs number of cells differential nonlinearity pgate rise time vs load capacitance
6 ltc1325 reg (pin 1): internal regulator output. the regulator provides a steady 3.072v to the internal analog circuitry and provides a temperature stable reference voltage for generating mcv, htf, ltf and thermistor bias voltages with external resistors. requires a 4.7 m f or greater bypass capacitor to ground. d out (pin 2): ttl data output signal for the serial interface. d out and d in may be tied together to form a 3-wire interface, or remain separated to form a 4-wire interface. data is transmitted on the falling edge of clk (pin 5). d in (pin 3): ttl data input signal for the serial interface. the data is latched into the chip on the rising edge of the clk (pin 5). cs (pin 4): ttl chip select signal for the serial interface. clk (pin 5): ttl clock for the serial interface. ltf (pin 6): minimum allowable battery temperature analog input. ltf may be generated by a resistive divider between reg (pin 1) and ground. mcv (pin 7): maximum allowable cell voltage analog input. mcv may be generated by a resistive divider be- tween reg (pin 1) and ground. htf (pin 8): maximum allowable battery temperature analog input. htf may be generated by a resistive divider between reg (pin 1) and ground. gnd (pin 9): ground. filter (pin 10): the external filter capacitor c f is con- nected to this pin. the filter capacitor is connected to the output of the internal resistive divider across the battery to reduce the switching noise while charging. in the gas gauge mode, c f along with an internal r f = 1k form a lowpass filter to average the voltage across the sense resistor. pi n fu n ctio n s uuu sense (pin 11): the sense pin controls the switching of the 111khz pwm constant current source in the charging mode. the sense pin is connected to an external sense resistor r sense and the negative side of the battery. the charging loop forces the average voltage at the sense pin to equal a programmable internal reference voltage v dac . the battery charging current is equal to v dac /r sense . in the gas gauge mode the voltage across the sense pin is filtered by an rc network (r f and c f ), amplified by an inverting gain of four, then multiplexed to the adc so the average discharge current through the battery may be measured and the total charge leaving the battery calculated. v in (pin 12): general purpose adc input. t amb (pin 13): ambient temperature input. connect to an external thermistor network. tie to reg if not used. may be used as another general purpose adc input. t bat (pin 14): battery temperature input. connect to an external ntc thermistor network. tie to reg if not used. v bat (pin 15): battery input. an internal voltage divider is connected between the v bat and sense pins to normalize all battery measurements to one cell voltage. the divider is programmable to the following ratios: 1/1, 1/2, 1/3 . . . 1/15, 1/16. in shutdown and gas gauge modes the divider is disconnected. dis (pin 16): active high discharge control pin. used to turn on an external transistor which discharges the battery. pgate (pin 17): fet driver output. swings from gnd to v dd . v dd (pin 18): positive supply voltage. 4.5v < v dd < 16v.
7 ltc1325 block diagra m w 10-bit a/d converter charge loop and gas gauge fault detect circuitry divider timeout logic to0 to to2 dr0 to dr3 3 t out 111khz oscillator duty ratio generator adc mux serial i/o 3.072v analog regulator 5v digital regulator analog and digital v dd adc reference control logic 3 ps gas gauge 4 div0 to div3 5 mod0 to mod1, vr0 to vr1, ps charge 11 sense 15 v bat 14 t bat filter pgate ltc1325 ?bd 10 17 6 ltf 8 htf 7 mcv t out 13 t amb 12 v in 10 2 d out d in cs gnd 3 4 clk 5 digital input circuits 9 v dd 18 ps, msbf 2 ds0 to ds1 sgl/diff 3 3 mod0 to mod1, ps 7 batp, batr, fmcv, fedv, fhtf, fltf, t out dis 16 reg 1 ps test circuits load circuit for t ddo , t r and t f load circuit for t dis and t en d out 3k 100pf test point 5v t dis waveform 2, t en t dis waveform 1 ltc1325 ?tc02 d out 1.4v 3k 100pf ltc1325 ?tc01
8 ltc1325 test circuits voltage waveforms for d out delay time, t ddo voltage waveforms for d out rise and fall times, t r , t f clk d out 0.8v t ddo 0.4v 2.4v ltc1325 ?tc03 0.4v 2.4v t r t f ltc1325 ?tc04 voltage waveforms for t en on and off channel leakage voltage waveforms for t dis d out waveform 1 (see note 1) t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by cs. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by cs. ltc1325 ?tc06 2v ltc1325 ?tc07 cs d in d out clk start 121222324 0.4v 0.4v d9 vr1 three-state null t en 3.072v a a i off i on off channels note: external channels only t bat , t amb and v in on channel ltc1325 ?tc05 }
9 ltc1325 ti i g diagra u w w start hi-z hi-z fs batp d1 d9 d0 msbf null cs clk d in d out command word msb-first data (msbf = 1) adc data status word start hi-z ltc1325 ?td hi-z fs batp d1 d1 d9 d9 d0 vr1 null cs clk d in d out command word note: the timing diagram shows two possible command words. refer to functional description for information on how to construct the command word adc data status word msb-first data (msbf = 0) general description during normal operation, a command word is shifted into the chip via the serial interface, then an adc measurement is made and the 10-bit reading and chip status word are shifted out. the command word configures the ltc1325 and forces it into one of five modes: power shutdown, idle, discharge, charge or gas gauge mode. in the power shutdown mode, the analog section is turned off and the supply current drops to 30 m a. the voltage regulator, which provides power to the internal analog circuitry and external bias networks, is shut down. the voltage divider across the battery is disconnected and only the voltage regulator for the serial interface logic is left on. during the idle mode, the chip is fully powered but the discharge, charge, and gas gauge circuits are off. the chip may be placed in the idle mode momentarily while charg- ing the battery, allowing an adc measurement to be made without any switching noise from the pwm current source affecting the accuracy of the reading. the mode command bits are picked off as they appear at d in , allowing the charging loop to turn off and settle while the remainder of the command word is being shifted in. fu n ctio n al descriptio uu u during the discharge mode, the battery is discharged by an external transistor and series resistor. the battery is monitored for fault conditions. in the charge mode, the m p monitors the batterys voltage, temperature and ambient temperature via the 10-bit adc. termination methods such as C d v bat , d v bat / d time, d t bat , d t bat / d time, d (t bat C t a ), maximum tempera- ture, maximum voltage and maximum charge time may be accurately implemented in software. the ltc1325 also monitors the battery for fault conditions. in the gas gauge mode, the average voltage across the sense resistor can be measured to determine the average battery load current. the sense voltage is filtered by an rc circuit, multiplied by an inverting gain of four, then con- verted by the adc. the m p can then accumulate the adc measurements and do a time average to determine the total charge leaving the battery. the rc circuit consists of an internal 1k resistor r f and an external capacitor c f connected to the filter pin.
10 ltc1325 bit 1: start bit (start) the first logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer and all leading zeros which precede this logical one will be ignored. after the start bit is received, the remaining bits of the command word will be clocked in. bits 2 and 3: mode select (mod0 and mod1) the two mode bits determine which of four modes the chip will be in: idle, discharge, charge or gas gauge. mod1 mod0 description 0 0 idle 0 1 discharge 1 0 charge 1 1 gas gauge bit 4: single-ended differential conversion (sgl/diff) sgl/diff determines whether the adc makes a single- ended measurement with respect to ground or a differen- tial measurement with respect to the sense pin. sgl/diff description 0 single-ended adc conversion 1 differential adc conversion (with respect to sense) command word the command word is 22 bits long and contains all the information needed to configure and control the chip. on power-up all bits are cleared to logical 0. fu n ctio n al descriptio uu u start = 1 1 mod0 2 mod1 3 sgl/ diff 4 msbf 5 ds0 6 ds1 7 ds2 8 div0 9 div1 10 div2 11 div3 12 ps 13 dr0 14 dr1 15 dr2 16 fsclr 17 to0 18 to1 19 to2 20 vr0 21 vr1 22 ltc1325 ?f01 figure 1. command word bit 5: msb-first/lsb-first (msbf) the adc data is programmed for msb-first or lsb-first sequence using the msbf bit. see serial i/o description for details. msbf description 0 lsb-first data follows msb-first data 1 msb-first data only bits 6 to 8: adc data input select (ds0 to ds2) ds2, ds1 and ds0 select which circuit is connected to the adc input. do not use unlisted combinations. ds2 ds1 ds0 description 0 0 0 gas gauge output 0 0 1 battery temperature pin, t bat 0 1 0 ambient temperature pin, t amb 0 1 1 battery divider output voltage, v cell 100v in pin bits 9 to 12: battery divider ratio select (div0 to div3) div3, div2, div1 and div0 select the division ratio for the voltage divider across the battery. div3 div2 div1 div0 description 0000(v bat C v sense )/1 0001(v bat C v sense )/2 0010(v bat C v sense )/3 0011(v bat C v sense )/4 0100(v bat C v sense )/5 0101(v bat C v sense )/6 0110(v bat C v sense )/7 0111(v bat C v sense )/8 1000(v bat C v sense )/9 1001(v bat C v sense )/10 1010(v bat C v sense )/11 1011(v bat C v sense )/12 1100(v bat C v sense )/13 1101(v bat C v sense )/14 1110(v bat C v sense )/15 1111(v bat C v sense )/16
11 ltc1325 fu n ctio n al descriptio uu u bits 21 and 22: charging loop reference voltage select (vr0 and vr1) vr1 and vr0 select the desired reference voltage v chrg for the charging loop. the charging loop will force the average voltage at the sense pin to be equal to v dac . the average charging current is v dac /r sense (see figure 4). vr1 vr0 v dac (mv) 0018 0134 1055 1 1 160 status word the status word is 8 bits long and contains the status of the internal fail-safe circuits. bit 1: battery present (batp) the batp bit = 1 indicates the presence of the battery. the bit is set to 1 when the voltage at the v bat pin falls below (v dd C 1.8v). batp = 0 when the battery is removed and v bat is pulled high by r trk (see figure 3). batp conditions 0(v dd C 1.8) < v bat < v dd 1v bat < (v dd C 1.8) bit 2: battery reversed (batr) or shorted the batr bit indicates when the battery is connected backwards or shorted. the bit is set when the battery cell voltage at the output of the battery divider v cell is below 100mv. batr conditions 0v cell > 100mv 1v cell < 100mv batp 1 batr 2 fmcv 3 fedv 4 fhtf 5 fltf 6 t out 7 fs 8 ltc1325 ?f02 figure 2. status word bit 13: power shutdown (ps) ps selects between the normal operating mode, or the shutdown mode. ps description 0 normal operation 1 shutdown all circuits except digital inputs bits 14 to 16: duty ratio select (dr0 to dr2) dr2, dr1 and dr0 select the duty cycle of the charging loop operation (not 111khz pwm duty cycle). the last three selections place the chip into a test mode and should not be used. dr2 dr1 dr0 description 0 0 0 1/16 0 0 1 1/8 0 1 0 1/4 0 1 1 1/2 1001 1 0 1 test mode 1 1 1 0 test mode 2 1 1 1 test mode 3 bit 17: fail-safe latch clear (fsclr) when fsclr bit is set to one, the internal fail-safe timer is reset to 0, and the fail-safe latches are reset. fsclr is automatically reset to 0 when cs goes high. fsclr description 0 no action 1 reset fail-safe timer and latches bits 18 to 20: timeout period select (to0 to to2) to2, to1 and to0 select the desired fail-safe timeout period,t out . on power-up, the default timeout is 5 minutes. to2 to1 to0 timeout (minutes) 0005 00110 01020 01140 10080 1 0 1 160 1 1 0 320 1 1 1 indefinite (no timeout)
12 ltc1325 fu n ctio n al descriptio uu u bit 3: maximum cell voltage (fmcv) the mcv bit indicates when the battery cell voltage has exceeded the preset limit. the bit is set when v cell is greater than the voltage at the mcv pin. fmcv conditions 0v cell < v mcv 1v cell > v mcv bit 4: end discharge voltage (fedv) the edv bit indicates when the battery cell voltage has dropped below an internally preset limit. the bit is set when the battery cell voltage at the output of the voltage divider v cell is less than 900mv. fedv conditions 0v cell > 900mv 1v cell < 900mv bit 5: high temperature fault (fhtf) the htf bit indicates when the battery temperature is too high. using a negative tc thermistor, the bit is set when the voltage at the t bat pin is less than the voltage at the htf pin. fhtf conditions 0t bat > v htf 1t bat < v htf bit 6: low temperature fault (fltf) the ltf bit indicates when the battery temperature is too low. using a negative tc thermistor, the bit is set when the voltage at the t bat pin is greater than the voltage at the ltf pin. fltf conditions 0t bat < v ltf 1t bat > v ltf bit 7: timeout (t out ) the t out bit indicates that the battery charging time has exceeded the preset limit. the bit is set when the internal timer exceeds the limit set by the command bits to0, to1 and to2. t out conditions 0 no timeout has occurred 1 timeout has occurred bit 8: fail-safe occurred (fs) the fs bit indicates that one of the fault detection circuits halted the discharging or charging cycle. the bit is set when an edv, ltf, htf, or t out fault occurs during discharge. during charging, the bit is set when a mcv, ltf, htf, or t out fault occurs. the bit is reset by the command word bit fsclr. fs conditions 0 no fail-safe has occurred 1 fail-safe has occurred detailed description fault conditions the ltc1325 monitors the battery for fault conditions before and during discharge and charge (see figure 3). they include: battery removed/present (batp), battery reversed/shorted (batr), maximum cell voltage exceeded figure 3. fail-safe or fault detection circuitry + + + v dd batp fmcv programmable battery divider c2 c1 1.8v c3 c4 + fedv + batr v dd v bat sense mcv 900mv 100mv t bat htf r4 r3 r l r t ltc1325 ?f03 ltf reg reg r trk r1 r2 3.072v linear regulator c5 + fhtf c6 + fltf
13 ltc1325 fu n ctio n al descriptio uu u the chip enters the discharge mode when the proper mode command bits are set and the power shutdown command bit is clear. if a fault condition does not exist, then the dis pin is pulled up to v dd by the internal driver. the dis voltage is used to turn on an external transistor which discharges the battery through an external series resistor r dis . discharging will continue until a new command word is input to change the mode or a fault condition occurs. charge mode command: mod1 = 1, mod0 = 0, ps = 0 status: batp = 1, batr = 0, fmcv = 0, fedv = x, fhtf = 0, fltf = 0, t out = 0 the chip enters the charge mode when the proper mode command bits are set and the power shutdown command bit is clear. if a fault condition does not exist then charging can begin. charging will continue until a new command word is input to change the mode or a fault condition occurs. the charge current may be regulated by a programmable 111khz pwm buck current regulator, or by using the pfet to gate an external current regulator or current limited transformer. 111khz pwm controller the block diagram of the charging loop connected as a pwm buck current regulator is shown in figure 4. the pwm may operate in either continuous or discontinuous mode. the loop forces the average voltage across the sense resistor to be equal to the voltage at the output of the dac, so that the charging current becomes v dac /r sense . with switch s2 on and the others off, amplifier a1 along with c1, r1 and r2 are configured as an integrator with 16khz bandwidth. the output of the integrator is the average difference between the voltage across the sense resistor and the dac output voltage. the rising edge of the oscillator waveform triggers the one shot which sets the flip-flop output high. this turns on the external pfet p1 by pulling its gate low via the fet driver. with p1 on, the current through the inductor l1 starts to (mcv), minimum cell voltage exceeded (edv), high tem- perature limit exceeded (htf), low temperature limit ex- ceeded (ltf) and time limit exceeded (t out ). when a fault condition occurs, the discharge and charge loops are disabled or prevented from turning on and the fail-safe bit (fs) is set. the chip is reset by shifting in a new command word with the fail-safe clear fsclr bit set. the 8-bit status word contains the state of each fault condition. power shutdown mode command: mod1 = x, mod0 = x, ps = 1 status: batp = x, batr = x, fmcv = x, fedv = x, fhtf = x, fltf = x, t out = x in the power shutdown mode, the analog section is turned off and the supply current drops to 30 m a. the voltage regulator, which provides power to the internal analog circuitry and external bias networks, is shut down. the voltage divider across the battery is disconnected and the only circuit left on is the voltage regulator for the serial interface logic. idle mode command: mod1 = 0, mod0 = 0, ps = 0 status: batp = x, batr = x, fmcv = x, fedv = x, fhtf = x, fltf = x, t out = x the chip enters the idle mode when the proper mode command bits are set and the power shutdown command bit is cleared. during the idle mode, the chip is fully powered, but the discharge, charge and gas gauge circuits are off. the chip may be placed in the idle mode momen- tarily while charging the battery, allowing an adc mea- surement to be made without any switching noise from the pwm current source affecting the accuracy of the reading. the mode command bits are picked off as they appear at d in , so that while the rest of the command word is being shifted in, the charging loop has time to settle before an adc measurement is made. discharge mode command: mod1 = 0, mod0 = 1, ps = 0 status: batp = 1, batr = 0, fmcv = x, fedv = 0, fhtf = 0, fltf = 0, t out = 0
14 ltc1325 fu n ctio n al descriptio uu u + + v dd 4.5v to 16v p1 irf9z30 n1 irfz34 r trk d1 1n5818 pgate dis discharge r f 1k r2 125k r1 500k reg 3.072v c1 16pf filter ltc1325 ?f04 sense s4 battery l1 r dis r sense c f s2 s1 s3 gg dr0 to dr2 a1 a2 gg 0 0 0 0 1 vr1 0 0 1 1 x vr0 0 1 0 1 x dac voltage 18mv 34mv 55mv 160mv 0mv dac vr0, vr1 gg (gas gauge) chip boundary 2 v dac r s q duty ratio generator one shot 111khz oscillator 3 charge to adc mux figure 4. charging loop block diagram rise as does the voltage across the sense resistor. when the voltage across the sense resistor is greater than the output of the integrator, comparator a2 changes state. this resets the flip-flop and p1 is turned off. catch diode d1 clamps the drain of p1 one diode drop below ground when the inductor flies back and the current through the inductor starts to drop. the voltage across the sense resistor also drops and may reach zero and stay there until the next clock cycle begins. the average charging current is set by the output of the dac (v dac ) and the duty ratio generator. v dac can be programmed to one of four values with the following ratios: 1, 1/3, 1/5 or 1/10. the duty ratio can be set to 1/16, 1/8, 1/4, 1/2 or 1. when the duty ratio is 1, the duty ratio generator output is always low and the charge loop operates continuously (see figure 4). at other duty ratio settings, the duty generator output is a square wave with a period of 42 seconds. the time for which the generator output is low varies with the duty ratio setting. for ex- ample, if a duty ratio of 1/2 is programmed, the generator output is low only for 42/2 = 21 seconds. since the loop operates for only 21 out of every 42 seconds, the average charging current is halved. in general, the average charg- ing current is: i chrg = v dac (duty ratio)/r sense gated pfet controller when using an external current regulator or current lim- ited wall pack, simply remove the inductor l1 and catch diode d1. set the dac control bits vr1 = 1 and vr0 = 1, and select the desired duty ratio. by insuring that the voltage at the sense pin is never greater than 140mv, the output of the integrator a1 will saturate high and the comparator a2 will never trip and turn the loop off. this can be achieved by removing the sense resistor and grounding the sense pin or if the gas gauge is to be used, selecting r sense so that r sense /i chrg < 140mv.
15 ltc1325 fu n ctio n al descriptio uu u gas gauge mode command: mod1 = 1, mod0 = 1, ps = 0 status: batp = x, batr = x, fmcv = x, fedv = x, fhtf = x, fltf = x, t out = x in the gas gauge mode, the average voltage across the sense resistor can be measured to determine the average battery load current. the output of the dac is set to ground and switches s1, s3 and s4 are closed. a1 is configured as an inverting amplifier with r1 and r2 setting the gain to C 4. the voltage across the sense resistor is filtered by an rc circuit (r f , c f ) amplified by a1, then converted by the adc. the microprocessor can then accumulate the adc mea- surements and do a time average to determine the total charge leaving the battery. the sense pin voltage should not be more negative than C 450mv to ensure linearity. the r f c f circuit consists of an internal 1k resistor and an external capacitor connected to the filter pin. r f c f should be longer than the measurement interval. with the serial clock running at 100khz, it take 380 m s to shift in the command word and shift out the adc measurement and status word. trickle resistor an external trickle resistor has several functions. first, it provides a continuous trickle charge current for topping off the battery and countering the effects of self-discharge. second, it can be used to condition a deeply discharged battery for charging. the ltc1325 will not charge a battery unless its cell voltage is above 100mv (batr). finally, the resistor is required by the battery detect circuit to pull the v bat pin high when the battery is removed. serial interface the ltc1325 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. the clock clk synchronizes the data transfer with each bit being transmitted on the falling edge and captured on the rising clk edge in both transmit- ting and receiving systems. the ltc1325 first receives input data and then transmits back the a/d conversion result and status word (half duplex). because of the half duplex operation, d in and d out may be tied together allowing transmission over just three wires: cs, clk and data (d in /d out ). data transfer is initiated by a falling chip select cs signal. after cs falls, the ltc1325 looks for a start bit on d in . the start bit is the first logical one clocked into the d in input after cs goes low. the ltc1325 will ignore all leading zeros which precede this logical one. after the start bit is received, the 21 other control bits are shifted into the d in pin to configure the ltc1325 and start a conversion. after the last command bit, the d out pin remains in three-state for one clock period before it is taken low for one null bit. following the null bit, the conversion results and the 8 status bits are shifted out on the d out pin. at the end of the data exchange, cs should be brought high. msb-first/lsb-first (msbf control bit) the output data of the ltc1325 is programmed for msb- first or lsb-first sequence using the msfb control bit. when msbf = 1, data will appear on d out in msb-first format. this is followed by the 8 status bits. logical zeros will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. when msbf = 0, lsb-first data will follow the msb-first data. regardless of the state of msbf, the status bits are always shifted out in the same order (see figure 2). accommodating microprocessors with different word lengths the ltc1325 will fill zeros indefinitely after the transmit- ted data until cs is brought high. at that time d out is disabled (three-stated). this makes for easy interfacing to mpu serial ports with different transfer increments including 4 bits (e.g., cop400) and 8 bits (e.g., spi and microwire/plus tm ). any word length can be accom- modated by the correct positioning of the start bit in the input word. operation with d in and d out tied together the ltc1325 can be operated with d in and d out tied together. this eliminates one of the lines required to microwire/plus is a trademark of national semiconductor corp.
16 ltc1325 fu n ctio n al descriptio uu u communicate with the microprocessor. data is transmit- ted in both directions on a single wire. the processor pin connected to this data line should be configurable as either an input or an output. the ltc1325 will take control of the data line and drive it low after the 23rd falling clk edge after the start bit is received. therefore the processor port must be switched to an input before this happens to avoid a conflict. power-up after shutdown when a control word with the ps bit set to one is written to the ltc1325, it enters shutdown mode in which the v dd supply current is reduced to 30 m a. in this mode the on- chip 3v regulator and all circuits powered off it are shut down. the only circuits that remain alive are d in , cs and clk input buffers. to take the ltc1325 out from shut- down mode, a high to low edge must be applied to the cs pin. either d in or clk must be low when cs is low to prevent a false control word from being transmitted to the ltc1325. the 3v output decays with a time constant of 300ms with c reg = 4.7 m f. the microprocessor should wait three seconds before applying a wake-up edge to the cs pin to ensure proper power-up. r rtt t to o =- ? ? ? ? ? ? exp b 11 (2) rr t t lto o o = - + ? ? ? ? b b 2 2 (3) b= - ? ? ? ? ? ? ? ? ? ? t t tt in r r o o t to (4) a= ? ? ? ? 1 r dr dt t t (5) a b = - t 2 (6) dv dt vt t t div div o o o = () - + ? ? ? ? ? b 2 1 2 (7) where, v div (t) is the output of the divider, v reg is the voltage at the reg pin (3.072v nominal), r t is the thermistor resistance at some temperature t, r to is the thermistor resistance at some reference temperature t o , b is a constant dependent on thermistor material, a is the temperature coefficient (in %/ c) of r t at t o , and all temperatures are in k (i.e., t c + 273) there are two assumptions in the derivation of the above equations. b is assumed to be constant and the tempera- ture coefficient of r l is small compared to that of the thermistor. most thermistor data sheets specify r to , b , r t /r to ratios for two temperatures, a , and tolerances for b and r to . given b , and r to , it is easy to calculate r l from equation temperature sensing ntc (negative temperature coefficient) thermistors the simplest method to sense temperature (battery or ambient) with an ntc thermistor is to use a voltage divider powered by the reg pin. this divider consists of a load resistor r l in series with a thermistor r t as shown in figure 3. for a given thermistor, there is a value of r l which makes v div (t) linear over a narrow but adequate temperature range. the easiest method (inflection point method) to calculate r l is to set the second temperature derivative of the divider output to 0. the equations relevant to this method are: vt v r r ft div reg l t () = + ? ? ? ? = () 1 1 (1)
17 ltc1325 applicatio n s i n for m atio n wu u u (3). alternatively, b may be calculated from the r t /r to ratio using equation (4) or from a , using equation (6). as a numerical example, consider the panasonic ert-d2fhl103s thermistor which has the following char- acteristics: 1. r t (25 c) = r to = 10k 2. a = C 4.6%/ c at t o = 25 c 3. ratio r 25 /r 50 = 2.9 using equation (4) and r 25 /r 50 = 2.9, b = (323 298)in (2.9)/(298 C 323) = 4099k. alternatively, using equation (6) and a = C 4.6%/ c, b = C (C 0.046)(298) 2 = 4085k. both values of b are close to each other. substituting b = 4085k into equation (3) gives r l = 10k [4085 C (2 298)]/[4085 + (2 298)] = 7.45k. the nearest 1% resistor value is 7.5k. figure 5 shows a plot of v div (t) measured at various temperatures for this thermistor with a 7.5k r l . figure 5. ert-d2fhl103s divider t = [2.605 C v div (t)]/ 0.034. the straight line approxima- tion is accurate to within 2 c over a temperature range of 5 c to 45 c, assuming 3% b and 10% r to tolerances. ptc (positive temperature coefficient) thermistors positive temperature coefficient (ptc) thermistors may be used in battery chargers that do not require accurate temperature measurements. the resistance vs tempera- ture characteristics of ptc exhibits a sharp increase at a selectable switch temperature t s . this sharp change is exploited in chargers which use tco (temperature cutoff) or d tco (difference between battery and ambient tem- perature). with tco termination, a voltage divider consist- ing of a ptc and a low temperature coefficient load resistor is connected between reg and gnd with the top end of the ptc at reg. the ptc is mounted on the battery to sense its temperature. the divider output is tied to t bat . when the switch temperature is reached, the ptc resistance increases sharply causing t bat to fall below htf. this causes an htf fault and charging is terminated. to imple- ment d tco termination, the load resistor can, in principle, be replaced by a matching ptc and the divider now responds to differences between battery and ambient temperature. with both tco and d tco terminations, the position of the battery temperature ptc can be swapped with the load resistor or ambient temperature ptc. in both cases, an ltf fault terminates charge when the trip point is reached. note that in practice, matched ptcs are not readily available and for d tco termination, ntc ther- mistors are recommended. hardware design procedure this section discusses the considerations in selecting each component of a simple battery charger (see figures 3 and 4). further applications assistance is provided in application note 64, using the ltc1325 battery manage- ment ic. 1. r sense : there are three factors in selecting r sense : a. ltc1325 v ref and duty ratio settings b. sense resistor dissipation c. i load (r sense ) < C 450mv for gas gauge linearity temperature ( c) ?0 0.5 divider output voltage (v) 0 1.0 1.5 2.0 4.5 3.0 ?0 20 40 ltc1325 ?f05 0.5 3.5 4.0 2.5 ?0 0 60 80 actual ideal there are two methods of calculating battery or ambient temperature from adc readings of the t bat or t amb channels. the first method is to store the v div (t) vs t curve as a lookup table. the second method is to use a straight line approximation. the equation of this line may be calculated from the slope dv div /dt at t o [see equation (7)] and assuming that the line passes through the point [t o , v div (t o )] on the curve. for the ert-d2fhl103s, the slope is minus 34mv/ c and the equation of the line is
18 ltc1325 applicatio n s i n for m atio n wu u u between the v bat and sense pins and the internal divider should be set to divide-by-1. the minimum v dd supply must be greater than the end-of-charge voltage v ec times the number of cells (n) in the battery plus drops across the on-resistance of the pfet, inductor (v l ), battery internal resistance r int and sense resistor r sense . minimum v dd should be the greater voltage of the results from these two equations: min v dd =i chrg [r ds(on) (p1) + r sense + n(r int )] + n(v ec ) + v l or, min v dd = n(v ec ) + 1.8v assuming v ec = 1.6v, the ltc1325 will charge up to 8 cells with a 16v supply. for a higher number of cells, an external level shifter and regulator are needed. in some applications, there are other circuits attached to the charging supply. when the charging supply (v dc ) is powered down or removed, the battery may supply current to these circuits through the pfet body diode. to prevent this, a blocking diode can be added in series with v dc as shown in the circuit in the typical application section. 3. inductor l: to minimize losses, the inductor should have low winding resistance. it should be able to handle expected peak charging currents without satu- ration. if the inductor saturates, the charging current is limited only by the total pfet r ds(on) , inductor winding resistance, r sense and v dd source resis- tance. this fault current may be high enough to damage the battery or cause the maximum power ratings of the pfet, inductor or r sense to be ex- ceeded. 4. catch diode d1: the catch diode should have a low forward drop and fast reverse recovery time to mini- mize power dissipation. total power loss is given by: p dd1 = v f ( i f ) + (v r )(f)(t rr )(i f ) the ltc1325 has five duty ratio and four v dac settings giving 20 possible charge rates (for a given value of r sense ) as shown in the following table. for any combination of v dac and duty ratio, the average charging current is given by: avg i chrg = v dac (duty ratio)/r sense normalized duty ratio v dac 1 1/2 1/4 1/8 1/16 1(vr1 = 1, vr0 = 1) 1 1/2 1/4 1/8 1/16 1/3(vr1 = 1, vr0 = 0) 1/3 1/6 1/12 1/24 1/48 1/5(vr1 = 0, vr0 = 1) 1/5 1/10 l/20 1/40 1/80 1/10(vr1 = 0, vr0 = 0) 1/10 1/20 1/40 1/80 1/160 note that the table entries give relative charge rates assuming that the vr1 = 1, vr0 = 1, duty ratio = 1 entry is equivalent to a 1c charge rate. therefore, the charge rate (in c-units) for other vr1, vr0, and duty ratio settings may be read directly from the table. in gen- eral, the vr1 = 1, vr0 = 1, duty ratio = 1 entry can be equivalent to any charge rate, say k times 1c. then all entries in the table should be multiplied by k. in general, v dac and duty ratio settings are changed by the microprocessor to charge batteries of different capacities or to alter charge rates when charging the same battery in several stages. for best accuracy, vr1 and vr0 should be set to 1 where possible. the power dissipation of the sense resistor varies between charge, discharge and gas gauge modes and should be calculated for all three modes. typically, dissipation is higher in discharge and gas gauge modes since batteries can deliver higher currents than they can be charged with. in gas gauge mode, the load current supplied by the battery should not exceed 450mv/r sense for the gas gauge to remain linear in response. r sense should be low enough to ensure that i load (r sense ) does not fall below ground by more than 1 diode drop. 2. v dd supply: v dd should be at least 1.8v above the maximum battery voltage to prevent a batp = 0 error when the ltc1325 is in charge or discharge mode. if this requirement cannot be met in a specific applica- tion, an external battery divider should be connected
19 ltc1325 applicatio n s i n for m atio n wu u u where, i f = forward diode current, i f = forward diode current just prior to turn off, v f = forward drop, v r = reverse diode voltage (approximately equal to v dd ), f = pwm frequency (111khz), and t rr = reverse recovery time the power and maximum reverse voltage ratings of the diode should be greater than p dd1 and v dd respectively. the catch diode should also have fast turn-on times to reduce the voltage glitch at its cathode when turning on. schottky diodes have fast switching times and low forward drops and are recommended for d1. 5. trickle resistor r trk : r trk sets the desired trickle current in the battery to compensate for self-dis- charge which is in the order 1% and 2% of capacity per day for nicd and nimh batteries respectively. trickle charge rates are typically in the c/30 to c/50 range, where c is battery capacity. i trk = (v dd C v bat )/r trk where v bat is the voltage of a full charged battery. note that i trk varies as the battery is being charged. 6. thermistor r t and load r l : the total resistance of the thermistor network should be greater than 30k at the high temperature extreme to minimize effects of load regulation (see reg pin loading). 7. fault setting resistors r1, r2, r3 and r4: the voltage levels at the ltf, htf and mcv pins are tapped from a resistor divider powered by the reg pin. the voltage levels are selected taking into account: a. manufacturer recommended temperature and voltage limits, b. loading on the reg pin (< 2ma) c. input voltage ranges of the ltf, htf and mcv comparators: 1.6v < v ltf , v mcv < 2.8v and 0.5v < v htf < 1.3v d. thermistor divider temperature curve typical temperature limits for both nicd and nimh batteries are shown below. battery type min max min max standard C 20 45 to 50 0 45 to 50 quick C 20 45 to 50 10 45 to 50 fast or rapid C 20 45 to 50 15 45 to 50 trickle C 20 45 to 50 0 45 to 50 note that the discharge limits are wider than the charge limits. to prolong battery life, manufacturers generally recommend discharge temperatures that are similar to the charge limits. for this reason, the ltc1325 recognizes the same ltf and htf limits in both charge and discharge modes. mcv should be set just above the charging voltage per cell given in battery specifications. the voltage at the ltf and htf pins should be set to correspond to narrowest tem- perature range. these are typically 15 c and 45 c. the corresponding voltages may be read from the thermistor divider temperature curve such as that shown in figure 5. for this thermistor, it works out to be about for 2.12v for ltf and for 1.13v for htf. the mcv may be conveniently tied to ltf since mcv is typically 2v. if desired, external analog switches under microprocessor control may be used to vary the ltf, htf and mcv voltages between modes or for different charge rates. the values of r1, r2, r3 and r4 in figure 3 can be calculated from the following equations: r4 = v htf (re/v reg ) r3 = v mcv (re C r4) r2 = v ltf (re) C (r3 + r4) r1 = re C (r2 + r3 + r4) where re = r1 + r2 + r3 + r4 is chosen to minimize loading on the reg pin. a minimum value of 30k is recommended. note that v ltf is assumed to be greater than v mcv . if this is not the case, v ltf and v mcv in the above equations should be swapped. if the mcv and ltf pins are shorted to the same point, r2 should be set to 0. charge temp range ( c) discharge temp range ( c)
20 ltc1325 applicatio n s i n for m atio n wu u u pfet to within the maximum gate source voltage rating of the latter. finally, d2 clamps v bat to 15v. charging batteries with voltages above 16v to charge a battery with a maximum (fully charged) voltage of above 16v, the charging supply v dc must be above 16v. thus the charger will need the regulator, level shifter and clamp mentioned in the previous section. in addition, an external battery divider must be added to limit the voltage at the v bat pin to less than v dd . this is shown in the typical application circuit, wide voltage battery charger. the resis- tors r9 and r10 are selected to divide the battery voltage by the number of cells in the battery and the battery divider internal to the ltc1325 is set to divide-by-1. the external divider prevents v bat from ever rising to v dd and this causes the batp (battery present flag) to be high regardless of whether the battery is physically present or not. this does not affect the other operations of the ltc1325. software design a general charging algorithm consists of the following stages: discharge before charge fast charge top off charge trickle charge under some operating and storage conditions, nicd and nimh batteries may not provide full capacity. in particular, repeated shallow charge and discharge cycles cause the memory effect in nicd batteries. in order to restore full capacity (battery conditioning), these batteries have to be subjected to several deep discharge/charge cycles which will be provided by repetitions of the above algorithm. figure 6 shows a simplified flowchart of a charging algo- rithm. in practice, this flowchart has to be augmented to take into account the occurrence of fail-safes at any point in the algorithm. for example, the battery temperature could rise above htf during discharging or charging. general programming notes are as follows: 1. the start bit is always high. 2. the sgl/diff bit is generally set to low so that the adc makes conversions with respect to ground. 8. reg pin loading: the 3.072v regulator has a load regulation specification of C 5mv/ma. since the adc uses the same regulator as reference, it is desirable to reduce loading effects on the reg pin especially over temperature. thermistors with r to values of at least 10k at 25 c are recommended. at 50 c, the ther- mistor resistance could drop by a factor of 3 from its value at 25 c. r l is chosen as explained in the section on temperature sensing. the temperature coefficient of r l is not critical since the thermistor tempco dominates the sensing circuit. 9. r dis : r dis is selected to limit the discharge current to a value within the battery discharge specifications and must have a power rating above i dis 2 (r dis ) where: i dis = v bat /[r dis + r ds(on) (n1)] 10. pfet(p1) and nfet(n1): for operation of the charge and discharge loops, ? v gs ? < v dd since the pgate and dis pins swing between 0 and v dd . ? v gs ? << v dd to minimize power dissipation. the power ratings of p1 and n1 should be above i chrg 2 [r ds(on) (p1)] and i dis 2 [r ds(on) (n1)] respectively. v ds(max) should be above v dd . charging from supplies above 16v in many applications, the charging supply is greater than the 16v maximum v dd rating of the ltc1325. the ltc1325 can easily be adapted to charge the batteries from a charging supply v dc that is above 16v by adding three external sub-circuits: 1. a regulator to drop v dc down to within the supply range of the ltc1325. 2. a level shifter between the pgate and the gate of the pfet, p1, to ensure that p1 can be completely turned off when pgate rises to v dd . 3. a voltage clamp on the v bat pin to prevent r trk from pulling v bat above v dd . the wide voltage battery charger circuit in the typical application section shows low cost implementations of all three sub-circuits. c1, r11 and d4 generate a 15v v dd for the ltc1325. d3, r12 and c2 form a level shifter. the zener d3 is chosen to clamp the source gate voltage of the
21 ltc1325 applicatio n s i n for m atio n wu u u 3. the msbf bit is set depending on whether the micro- processor clocks in serial data with msb- or lsb-first. 4. the ds0 to ds2 bits can be anything except when entering idle mode or when requesting for adc read- ings. in these cases, ds0 to ds2 are set to select the desired reading: t bat , v cell or t amb . 5. the ps bit should always be 0 so that the ltc1325 does not go into shutdown mode. 6. the dr0 to dr2 should not select any of the test modes. it may assume different settings between fast charge and top off charge in order to alter the charging current. 7. the fsclr bit should be set to 1 to clear any faults and reset the timer when starting discharge, fast charge or top off. the status bits that the ltc1325 returns during the same i/o operation (that fsclr is set to 1) should be checked to determine if faults were indeed cleared, i.e., discharging or charging has begun. this is not shown in the simplified flowchart of figure 6. for commands other than the start commands, fsclr should be set to 0 so as not to reset the timer. 8. the to0 to to2 bits should all be set to 1 in discharge mode to ensure discharge does not end prematurely due to a timeout fault. during fast charge or top off charge, these bits are set to a value suitable for the charge rate used. for example, if the charge rate is 1c, the timeout period should be set to 80 minutes. 9. in charge mode, the c f capacitor filters the v cell node and sees a small ripple due to ripple at the sense pin. prior to taking an adc reading, the ltc1325 is put in figure 6. simple charging algorithm conditioning? edv = 1? terminate? more conditioning? terminate? start end start discharge read status start fast charge idle mode and wait resume fast charge idle mode resume top off charge wait start top off charge read adc and status read adc and status wait no yes no yes no yes yes no no yes ltc1325 ?f06 wait idle mode and wait
22 ltc1325 wiper on a potentiometer between these two. table 1 illustrates a complete 6-byte exchange. note that the first byte is padded with zeroes to align the a/d data and status with byte boundaries. spcr = (spie = 0, spe = 1, dwom = 0, mstr = 1, cpol = 0, cpha = 0, spr1 = 0, spr0 = 1) ddrd = (bit7 = 0, bit6 = 0, ddr5 = 1, ddr4 = 1, ddr3 = 1, ddr2 = 0, ddr1 = 0, ddr0 = 1) table 1. 6-byte exchange spi communication with ltc1325 0 byte #1 tx 0 ss sck mosi portd.0 miso 00 0 0 start mod0 x byte #1 rx x xx x x x x mod1 byte #2 tx sgl/ diff msbf ds0 ds1 ds2 div0 div1 x byte #2 rx x xx x x x x div2 byte #3 tx div3 ps dr0 dr1 dr2 fsclr to0 byte #3 rx x x xx x x x x to1 byte #4 tx to2 vr0 vr1 0 0 0 0 x byte #4 rx x xx x 0 d9 d8 x byte #5 tx x xx x x x x d7 byte #5 rx d6 d5 d4 d3 d2 d1 d0 x byte #6 tx x xx x x x x batp byte #6 rx batr fmcv fevd fhtf fltf t 0ut fs ltc1325 ?ai01 clk d in cs d out 68hc11 5v ltc1325 x = dont care idle mode to minimize noise. the microprocessor should either disregard readings or wait for a second or so before taking a reading. this is to allow v cell to decay to the correct cell voltage. the worst case time constant is 150k w (c f ). 10. prior to the first start command, the battery divider setting may be incorrect so that c f may charge to a voltage that causes edv, batr or mcv faults. the worst case time constant is as in (9). the micropro- cessor should check faults during the transmission of a start command and resend the start command again when c f has been given enough time to charge up to the correct value. microprocessor interfaces the ltc1325 can interface directly to either synchronous, serial or parallel i/o ports of most popular microproces- sors. with a parallel port, 3 or 4 i/o lines can be pro- grammed to form a serial link to the ltc1325. motorola spi (68hc11) the 68hc11 has a dedicated synchronous serial interface called the serial peripheral interface (spi) which transfers data with msb-first and in 8-bit increments. to communicate with this microprocessor, the ltc1325 msbf control bit should be set to 1. the spi has four lines: master in slave out (miso), master out slave in (mosi), serial clock (sck) and slave select (ss). the 68hc11 is configured as a master by tying the ss line high. a control byte is written to the serial peripheral control register (spcr) to select master mode, set baud rate and clock timing relationship. another byte is written to the port d direction register (ddrd) to set mosi, sck and bit 0 (cs of ltc1325) as outputs. the 68hc11 clocks in data from the ltc1325 simultaneously under the control of sck. the microprocessor transmits the ltc1325 command word in 4 bytes. this is followed by 2 more dummy bytes (with all bits set low) in order to clock in the remaining ltc1325 adc and status bits. this software example allows you to verify communica- tions with the ltc1325. the command word configures the ltc1325 to perform an a/d conversion on the general purpose v in input. v in can be tied to gnd or reg or to a applicatio n s i n for m atio n wu u u
23 ltc1325 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. label mnemonic operand comments ldaa #$51 write control byte to the spcr staa $1028 ldaa #$39 setup port d ddrd staa $1009 port d bit 0 is cs ldx #$1000 load port base addr cslow bclr $08,x,#$01 take cs low ldaa #$02 send byte #1 (msb) with staa $102a start bit loop1 tst $1029 check for spi transfer bpl loop1 complete bit ldaa #$24 send byte 2 staa $102a loop2 tst $1029 check for spi transfer bpl loop2 complete bit ldaa #$03 send byte 3 staa $102a loop3 tst $1029 check for spi transfer bpl loop3 complete bit ldaa #$c0 send byte 4 staa $102a typical applicatio n u label mnemonic operand comments loop4 tst $1029 check for spi transfer bpl loop4 complete bit ldaa $102a get a/d high byte anda #$03 mask off unwanted bits staa hidata store in user memory ldaa #$00 send dummy byte #1 staa $102a loop5 tst $1029 check for spi transfer bpl loop5 complete bit ldaa $102a get a/d low byte staa lodata store in user memory ldaa #$00 send dummy byte #2 staa $102a loop6 tst $1029 check for spi transfer bpl loop6 complete bit ldaa $102a get status byte staa status store in user memory bset $08,x,#$01 raise cs high bra cslow loop for continuous readings applicatio n s i n for m atio n wu u u wide voltage battery charger note 1: needed when v dc > 16v or maximum battery voltage, v bat > 16v. note 2: regulator. omit this block and short vdd to v dc when v dc < 16v. note 3: level shifter. omit this block and short pgate to p1 gate when v dc < 16v. 1325 ta02 note 7: optional diode to prevent battery drain when the charging supply is powered down (see section 2, hardware design procedure). r sense p1 irf9z30 v dc 25v r8 100 w c f 1 m f v dd pgate dis v bat t bat t amb v in sense filter reg d out d in cs clk ltf mcv htf gnd r1 r11 220 1/2w r2 r3 r4 + c reg 4.7 m f mpu (e.g. 8051) p1.4 p1.3 p1.2 + c1 1 m f c2 0.1 m f r13 r6 r trk v bat r dis n1 irf830 c3 500pf therm 2 r5 ltc1325 therm 1 r7 l1 62 m h r9 note 5 note 3 note 1 note 1 note 2 r10 d1 1n5818 d3 1n4740a d4 1n4744a 15v r12 100k note 1 note 4 d2 1n4744a 15v note 6 + c4 22 m f r14 100 w mbr320 note 7 c5 0.1 m f note 4: zener to clamp v bat to below v dd . omit when v dc < 16v. note 5: external battery divider. needed when maximum battery voltage, v bat > 16v. note 6: v in is an uncommitted a/d channel.
24 ltc1325 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0895 2k rev a ? printed in usa ? linear technology corporation 1994 package descriptio n u dimension in inches (millimeters) unless otherwise noted. n package 18-lead plastic dip s package 18-lead plastic sol sw18 0695 see note 0.447 ?0.463* (11.354 ?11.760) 15 14 13 12 11 10 16 9 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 17 18 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options the part may be supplied with or without any of the options. dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** related parts part number description comments lt ? 1510 constant voltage/constant current battery charger 1.3a, li-ion, nicd, nimh, pb-acid charger lt1512 sepic constant current/constant voltage battery charger 0.75a, v in greater or less than v bat n18 0695 0.015 (0.381) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.255 0.015* (6.477 0.381) 0.900* (22.860) max 18 12 3 4 56 7 8 9 10 11 12 13 14 16 15 17 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)

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